Dynamic amplifier circuit

ABSTRACT

A dynamic amplifier circuit, specifically for switched-capacitor filters, having a current source which supplies an exponentially-decreasing bias current. In addition, a current source is included for supplying an additional bias current in order to define the minimum bias current in the amplifier circuit.

BACKGROUND OF THE INVENTION

The invention relates to a dynamic amplifier circuit for amplifying asignal in a first time interval, under control of a clock signal, whichcircuit comprises a bias circuit for obtaining a bias current in theamplifier circuit during said first time interval, which bias currentdecreases from an initial value. Such dynamic amplifier circuits areinter alia used in switched capacitor filter circuits in order to obtainthe filter action and have been proposed in order to replace operationalamplifiers in such circuits in inter alia:

Copeland, M. A. and Rabaey, J. M.: "Dynamic amplifier for M.O.S.technology", Electronics Letters, 1979, Vol. 15, No. 10, pages 301-302,

Hosticka, B. J.: "Dynamic amplifiers in C.M.O.S. technology",Electronics Letters, 1979, Vol. 15, No. 25, pages 819-820, and

Hosticka, B. J.: "Dynamic C.M.O.S. amplifiers" I.E.E.E. Journal ofSolid-State Circuits, Vol. SC-15, No. 5, pages 887-894; whichpublications are herewith incorporated by reference.

The advantage of such a dynamic amplifier circuit is that at thebeginning of the amplifying period, i.e. said first time interval, thebias current of the amplifier circuit is large, which means a highamplifier circuit speed at the beginning of the amplifying period, andthat at the end of the amplifying period the bias current is small,which means a high gain and hence a high accuracy at the end of theamplifying period.

A switched-capacitance arrangement comprising such dynamic-amplifiercircuits is found to be highly susceptible to interference, inparticular at the end of the first time interval, when the bias currentmay be very small, and during a subsequent time interval in which theamplifier is turned off. Moreover, it has been found that such amplifiercircuits present problems when a capacitance, for example the inputcapacitance of a following stage, is arranged between the outputs of twosuch dynamic amplifier circuits.

SUMMARY OF THE INVENTION

It is an object of the invention to provide a dynamic amplifier circuitof the type mentioned above, which does not have the disadvantagesmentioned above. The invention is based on the recognition that theseproblems arise because the final value of the bias current is undefined,or the bias current even decreases to substantially zero and theamplifier no longer operates. This occurs within the first time intervalunless the initial value of the decreasing bias current is madeextremely high in view of the various parameter spreads and therelationship between the initial value and the final value, which isgenerally not desirable. The invention is characterized in that the biascircuit comprises an additional source for obtaining a current in theamplifier circuit, which current is substantially constant relative tosaid bias current and which has a comparatively small value relative tosaid initial value in order to define the minimum bias current in theamplifier circuit at the end of said time interval.

A dynamic amplifier circuit in accordance with the invention, in whichthe bias circuit comprises a switched capacitance which is switched insuch a way that said capacitance is charged during a time intervalpreceding the first time interval and is discharged during the firsttime interval in order to obtain said variation, may further becharacterized in that a current source is arranged in a circuit which isparallel to the circuit comprising the switched capacitance.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described in more detail, by way of example, withreference to the drawing, in which:

FIG. 1a shows a first embodiment of a dynamic amplifier circuit usingthe invention;

FIG. 1b shows some diagrams to explain the operation of the circuitshown in FIG. 1a;

FIG. 1c shows a modified part of the circuit shown in FIG. 1a;

FIG. 2a shows a second embodiment of a dynamic amplifier circuit usingthe invention;

FIG. 2b shows some diagrams to explain the operation of the amplifiercircuit shown in FIG. 2a; and

FIG. 3 shows a third embodiment of a dynamic amplifier circuit using theinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The embodiment shown in FIG. 1a is based on the dynamic amplifiercircuits as inter alia described in the publication by B. J. Hosticka inElectronics Letters 1979, Vol. 15, pages 819-820 and it comprises anamplifier circuit with input transistors T₁ and T₂ arranged adifferential pair, whose gate electrodes are connected to the inputterminals 1 and 2. An output signal current is coupled to an output 3 bymeans of a current mirror comprising the transistors T₃ and T₄. A tailcurrent is applied to the source electrodes of the transistors T₁ and T₂by means of a transistor T₅, which together with a transistor T₆, whosedrain electrode is connected to the gate electrode, is arranged as acurrent mirror. For biasing the amplifier the drain electrode oftransistor T₆ is connected to the positive supply line 4 via acapacitance C₁. In parallel with this capacitance a switch 5 isarranged, which is switched by a signal Q, and between the capacitanceC.sub. 1 and the drain electrode of transistor T₆ a switch 6 isarranged, which is activated by a signal Q.

FIG. 1b represents the signals Q and Q. Prior to the instant t₁ switch 6is open and switch 5 is closed. Capacitance C₁ is then discharged. Atthe instant t₁ switch 6 is closed and switch 5 opens. Capacitance C₁ isthen charged via transistor T₆, resulting in an exponentially decreasingcharging current, which gives rise to to a tail current I of thedifferential pair, which current is represented as the current I_(a) inFIG. 1b. After some time the current I_(a) has decreased so far that thedifferential pair T₁, T₂ can no longer operate as an amplifier. Fromthis instant the circuit comprising such a dynamic amplifier becomeshighly susceptible to interference such as clock crosstalk andcapacitive signal transfer. If an output circuit, for example the inputcapacitance of a following stage, is arranged to be floating between twooutputs 3 of two dynamic amplifiers as shown in FIG. 1a, this will giverise to problems because the two amplifiers are not turned offsimultaneously. Increasing the initial current I_(a) (at instant t₁) isnot a remedy, because taking into account the exponential relationshipbetween the initial value and the final value and various parameterspreads, such as the value of the capacitance C₁ and the impedance valueof the transistor T₆, and taking into account the minimum clockfrequency, i.e. the maximum duration of the period t₁ -t₂, said initialcurrent value would have to be extremely high and the final value of thecurrent is undefined and in many cases higher than desirable.

According to the invention this problem can be solved by arranging acurrent source in parallel with capacitance C₁, which in the circuitshown in FIG. 1a is formed by a transistor T₇ having its gate and drainelectrodes interconnected. The resulting tail current I is thenrepresented by I_(b) in FIG. 1b, transistor T₇ defining the minimumvalue of the current I_(b) at the instant t₂. At this instant t₂ switch6 is opened and the current I ceases. For various uses, as in thecircuit shown in FIG. 1c, or when the circuit remains susceptible tointerference after the instant t₂, it may be desirable to keep theamplifier operative after the instant t₂ (and before the instant t₁) byproviding a minimum bias current. This may inter alia be achieved byconnecting the source electrode of transistor T₇ to the other side ofswitch 6 as represented by broken lines in FIG. 1a. The current I_(o)supplied by transistor T₇ is then sustained after the instant t₂, asrepresented by I_(c) in FIG. 1b.

Instead of arranging the current source (T₇) in the input circuit of thecurrent mirror T₅, T₆, this source may be arranged at other locations,such as between the source electrodes of the differential pair T₁, T₂and the negative power supply line 10, which is represented by thesource 7 in FIG. 1a.

In the circuit shown in FIG. 1a the amplifier is actuated during thephase Q by, for example, reading out a capacitive signal source, forexample, present in switched capacitance filters. During the phase Q theamplifier is not active and it may be set to a minimum bias currentI_(o). In specific cases it may occur that, for example by the alternateconnection to different input signal sources, the amplifier could beactive in both phases Q and Q. The exponentially decreasing bias currentwould then be available in both phases. This can be achieved byextending the input circuit of the current mirror T₅, T₆, as indicatedin FIG. 1c. In this extended circuit a second capacitance C₂ in serieswith a switch 8, which is switched by the signal Q, is arranged betweenthe drain electrodes of transistor T₆ and the positive power supply line4. In parallel with the capacitance C₂ a switch 9 is arranged, whichswitch is switched by the signal Q. During the phase Q (between theinstants t₁ and t.sub. 2 in FIG. 1b), in which capacitor C₁ provides thebias current for the differential pair T₁, T₂, capacitance C₂ isshort-circuited by the switch 9. At the instant t₂ switch 9 is openedand switch 8 is closed, while switch 6 opens. During the phase Qcapacitance C₂ provides the bias current for the differential pair T₁,T₂, so that also during this phase Q an exponentially decreasing biascurrent is obtained. This bias current is represented in FIG. 1b by thecharacteristic I_(d). The constant bias current I_(o) is then suppliedby transistor T₇ during both phases Q and Q since transistor T₇ isconnected to the drain electrode of transistor T₆.

FIG. 2a shows an embodiment of a dynamic amplifier circuit in accordancewith the invention, which embodiment is based on the dynamic amplifiercircuit as described by Messrs. M. A. Copeland and J. M. Rabaey inElectronics Letters, 10-5-1979, Vol. 15, No. 10, pages 301-302, whileFIG. 2b represents some signal waveforms to explain the operation ofthis dynamic amplifier circuit.

The dynamic amplifier circuit shown in FIG. 2a comprises a transistor T₈in a common-source arrangement, whose gate electrode constitutes theinput terminal 11. The drain electrode is connected to an outputterminal 13 via a switch 12 which is switched by a signal Q_(b), whichoutput terminal is connected to a positive power supply line 15 via aswitch 14 which is switched by a signal Q_(a) and to the gate electrodeof transistor T₈ via a capacitance C₃. An input circuit comprises acapacitance C₄, of which one side is connected to ground and of whichthe other side is connected to the gate electrode of transistor T₈ via aswitch 16 which is switched by a signal Q and to a signal input 18 via aswitch 17 which is switched by a signal Q.

In the period prior to the instant t_(o) (FIG. 2b) switches 12, 14 and16 are opened and switch 17 is closed in conformity with the signals Q,Q, Q_(a) and Q_(b). Capacitor C₄ is then charged in accordance with asignal voltage on input 18. At instant t_(o) switch 17 opens andswitches 14 and 16 close. Via switch 14 the series arrangement of thecapacitances C₃ and C₄ is then charged to the supply voltage, the chargedistribution between the capacitances C₃ and C₄ being determined by theamount of charge supplied to the capacitor C₄ prior to the instantt_(o). At instant t₁ switch 14 opens and switch 12 closes. CapacitancesC₃ and C₄ are then discharged via the drain-source path of transistorT₈, which capacitances then serve as charge sources for the currentthrough this transistor. Discharging stops at the instant that thevoltage on the gate electrode of transistor T₈ has reached the thresholdvoltage of this transistor. The residual charge across capacitor C₃ thendepends on said initial charge distribution and consequently on thesignal on input 11 and it determines the output voltage on output 13.The instant at which transistor T₈ is turned off depends on variousparameters, so that these parameters should be selected so thatdischarging is effected within the period Q. This results in the currentI through transistor T₈ as represented by I_(a) in FIG. 2b; anexponentially decreasing current which decreases to zero within the Qphase, which gives rise to the various aforementioned problems. Inaccordance with the invention a current source, in the presentembodiment in the form of a transistor T₉ having its gate and drainelectrodes interconnected, is arranged between output 13 and thepositive power supply line 15. If this current source carries a currentI_(o), discharge stops when the current I (I_(b) in FIG. 2b) throughtransistor T₈ has reached a value equal to I_(o).

In order to ensure that during the Q phase a current I_(o) is obtainedthrough transistor T₈, the current source T₉ may be arranged between thedrain electrode of transistor T₈ and the positive power supply line 15instead of between output 13 and the positive power supply line 15. Thecurrent I which then flows through transistor T₈ is represented by I_(c)in FIG. 2b.

FIG. 3 shows a variant of the circuit shown in FIG. 2a, which alsoutilizes the invention. In the circuit shown in FIG. 2a the capacitanceC₄ is charged to the input voltage V_(in) during phase Q and isdischarged to the threshold voltage V_(t) of transistor T₈ during phaseQ_(b), so that the charge transfer is equal to (V_(in) -V_(T)) C₄, whichcharge transfer is process-dependent as a result of the dependence onthe threshold voltage V_(T). As a result of the addition of thecurrent-source transistor T₉, what has been said regarding the thresholdvoltage V_(T) then applies to the source-gate voltage of transistor T₈for the current I_(o).

In the embodiment shown in FIG. 3, as compared with the embodiment shownin FIG. 2a, a capacitance C₅ is arranged between input terminal 11 andthe gate electrode of transistor T₈. Terminal 11 is, moreover, connectedto a source of reference voltage V_(ref) via switch 19, which switch isswitched by the signal Q. The gate electrode of transistor T₈ isconnected to the drain electrode of transistor T₈ via a switch 20 whichis switched by a signal Q_(c) and to the positive power supply line 15via a switch 21 which is controlled by a signal Q_(d). Thecurrent-source transistor T₉ is arranged between the positive powersupply line 15 and the drain electrode of transistor T₈.

During phase Q, in which capacitance C₁ is charged to the input voltageV_(in) one side of capacitance C₅ is connected to the reference voltageV_(ref) via switch 19. During this phase Q, switch 21 is initiallyclosed via signal Q_(d), so that transistor T₈ is turned on, andsubsequently switch 20 is closed and switch 21 is opened, so that thatside of the capacitance C₅ which is connected to the gate electrode oftransistor T₈ assumes a voltage V_(o) by discharging this capacitancevia transistor T₈, which voltage is the gate-source voltage oftransistor T₁ at the current I_(o). At the beginning of phase Q,capacitance C₅ then carries a voltage V_(ref) -V_(o). During phase Q thesituation is the same as in the circuit shown in FIG. 2a with theadditional feature that between capacitance C₄ and the gate electrode oftransistor T₈ a capacitance charged to a voltage (V_(ref) -V_(o)) ispresent. During phase Q , discharging of capacitance C₄ continues untilthe gate electrode of transistor T₈ carries the voltage V_(o)corresponding to the current I_(o), at which voltage the voltage acrosscapacitance C₄ is equal to the reference voltage V_(ref). As a result ofthis, the charge transfer via capacitance C₄ has become independent ofthe process-dependent voltage V_(o).

The reference voltage V_(ref) may alternatively be a signal voltage. Inthat case the circuit may be constructed as a differential integrator.

What is claimed is:
 1. A dynamic amplifier circuit for amplifying asignal in a first time interval under control of a clock signal, whichcircuit comprises a bias circuit for obtaining a bias current in theamplifier circuit during said first time interval, which bias currentdecreases from an initial value, characterized in that the bias circuitcomprises an additional source for obtaining a current in the amplifiercircuit, which current is substantially constant relative to said biascurrent and has a comparatively small value relative to the said initialvalue in order to define the minimum bias current in the amplifiercircuit at the end of said time interval.
 2. A dynamic amplifier circuitas in claim 1, in which the bias circuit comprises a switchedcapacitance and means for charging said capacitance during a timeinterval preceding the first time interval and for discharging saidcapacitance during the first time interval in order to obtain thevariation in said bias circuit, characterized in that a current sourceis provided in parallel with the circuit comprising the switchedcapacitance.